With the evolution of digital data communications, there seems to be a continual demand for data processing devices that may be capable of handling more data and with faster throughput.
At the same time, the semiconductor industry seems to continually strive to build integrated circuits of greater density and smaller size. But these increased levels of integration and functionality have placed a greater premium on the availability of signal interfacing.
To ease some of the effects of reduced I/O real estate, some manufacturers of high-speed data communication devices have developed transceivers (transmitters-receivers) with parallel-to-serial and serial-to-parallel data multiplexing/de-multiplexing circuit designs. By using these multiplexing circuits, the high-pin count, parallel data interfaces may be replaced with lower pin count, high-speed serial data interfaces. On a receiver side of a transceiver, for example, a high-speed serial data sequence may be received from an I/O link and then converted into parallel data of a slower clock rate. Conversely, on the transmission side of the transceiver, parallel data of a low-clock rate may be converted from the parallel format into a higher-speed, serial format.
These high speed transceiver-multiplexers may be described as Multi-Gigabit Transceivers (MGT) and may handle serial bit streams with transfer speed as high as 3-10 gigabits per second, or even higher. The serial-to-parallel format conversion or de-multiplexing provided by these transceivers, however, may effectively reduce the high-speed data rate of the serial link to a slower cycle rate to accommodate performance levels of more customary, lower cost technology as may be associated with common embedded processors or memory.
For a serial bit stream encoded with, e.g., an 8 bit/10 bit “non-return to zero” encoding and comprising a bit transfer rate of 3 gigabits per second (Gbs), receiver decode and clock recovery processes may convert the encoded 10 bits to 8 bits. This 10B/8B decode in combination with serial-to-parallel conversion for 16 bits parallel data may establish an effective internal data handling cycle rate of about 150 MHz.
To further enhance the data transfer capacity of a given communication channel, a plurality of serial data transceivers may be disposed in parallel relationships to interface multiple serial lanes for the communication channel. Such augmentation can benefit a variety of different large data capacity applications as may be utilized by embedded data/video processors or memory, e.g., which may be embedded in a programmable logic device such as a field programmable gate array (FPGA).
When transferring information across a serial data interface, the data may be segmented into one or more data frames. A start of frame character may signal a starting byte to a given group of data. The transfer may then continue with multiple bytes of data within one or more words until an end of frame character may signal the end of the data frame. The framed data accordingly resides between the Start-Of-Frame (SOF) character and the End-Of-Frame (EOF) character and may comprise a multiple number of bytes of a single or of multiple words therebetween.
In a serial data transfer, the data bits for the SOF, data and EOF characters may be transferred in serial sequential manner. But when presenting the data to a processor or memory within a system, the start and end signals may be removed from before and after the data of the serial sequence, and may be presented in parallel accompanying sideband signals.
For a communication channel comprising a single serial lane, the removal of control characters and collection and/or storage of real data between the SOF and EOF characters may be performed with relative ease. Once a SOF character is determined, real data may be retrieved byte-by-byte and collected for presentment or storage (assuming it has been distinguished from idle characters) as it is received until determining receipt of an EOF character.
In the case of a communication channel that may comprise multiple serial data lanes, the collection and/or storage of the real data may become more cumbersome given that the SOF and the EOF characters could appear on any one of the channel lanes and given that they could appear within a signal word or across multiple words. In this context, “word” may reference a plurality of bytes. The word may comprise a width of a given number of bytes proportional the number of lanes that make-up the communication channel. Thus, the process for organizing the recovered data bytes for subsequent presentment or storage may vary depending on the placement of the SOF (and EOF) characters and the placement of the recovered data bytes in the data word(s) relative to the determined SOF character.